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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* include/linux/platform_data/pxa_sdhci.h
*
* Copyright 2010 Marvell
* Zhangfei Gao <zhangfei.gao@marvell.com>
*
* PXA Platform - SDHCI platform data definitions
*/
#ifndef _PXA_SDHCI_H_
#define _PXA_SDHCI_H_
/* pxa specific flag */
/* Require clock free running */
#define PXA_FLAG_ENABLE_CLOCK_GATING (1<<0)
/* card always wired to host, like on-chip emmc */
#define PXA_FLAG_CARD_PERMANENT (1<<1)
/* Board design supports 8-bit data on SD/SDIO BUS */
#define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2)
/*
* struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
* @flags: flags for platform requirement
* @clk_delay_cycles:
* mmp2: each step is roughly 100ps, 5bits width
* pxa910: each step is 1ns, 4bits width
* @clk_delay_sel: select clk_delay, used on pxa910
* 0: choose feedback clk
* 1: choose feedback clk + delay value
* 2: choose internal clk
* @clk_delay_enable: enable clk_delay or not, used on pxa910
* @max_speed: the maximum speed supported
* @host_caps: Standard MMC host capabilities bit field.
* @quirks: quirks of platfrom
* @quirks2: quirks2 of platfrom
* @pm_caps: pm_caps of platfrom
*/
struct sdhci_pxa_platdata {
unsigned int flags;
unsigned int clk_delay_cycles;
unsigned int clk_delay_sel;
bool clk_delay_enable;
unsigned int max_speed;
u32 host_caps;
u32 host_caps2;
unsigned int quirks;
unsigned int quirks2;
unsigned int pm_caps;
};
#endif /* _PXA_SDHCI_H_ */
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